Monarch: A Platform for Logic Optimization using ATPG/Diagnosis-based Design Rewiring

In a typical VLSI design cycle, technology-dependent logic optimization may occur after the physical synthesis to satisfy various design constraints in area, power, timing, and testability. Recently, it is proposed in [7] an ATPGbased design rewiring methodology that achieves significant performance gains in benchmark circuits that are already optimized by formal techniques. This case study describes an application of this technique as a logic optimization platform for Motorola high-performance designs: Monarch. The flow, which consists of EDA vendor tools and inhouse software, allows the design error diagnosis and correction techniques of [7] to be applied to gate-level modules in high-performance cores. Experiments in timing optimization show that Monarch can improve the slack of a module that has been already optimized by tools from commercial EDA vendors.